Stats

  • Locked Locked
  • Replies 6
  • Subscribers 92
  • Views 15215
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Gated flop count

kazad

Hi

I am trying to get the no. of gated flop count within Encounter.

Can anyone throw any idea/procedure on this?

Thanks

Khandaker

  • Vishnu Chada
    sizeof_collection [get_cells -hier -filter " is_integrated_clock_gating_cell == true"]
  • grasshopper

     Hi Khandaker,

     

    I think this is what you want

        unset -nocomplain designMetrics

       dbForEachCellInst [dbHeadTopCell] inst {

            if {[dbIsInstStdCell $inst] && [dbIsCellSequential $cell]} {
                set designMetrics(seqArea) [expr $designMetrics(seqArea) + ${instArea}]
                incr designMetrics(seqCount)
            }
        }

     

    good luck,

    gh-

  • Vishnu Chada

    proc GateFlopCnt { } {
    set x  [get_cells -hier  -filter  " is_integrated_clock_gating_cell == true"]
    set cnt 0
    foreach_in_collection y $x {
           set inst [filter_collection [all_fanout -from [get_object_name $y]/Q -endpoints_only] { is_integrated_clock_gating_cell == true }]
            foreach_in_collection i $inst {
                     incr cnt
                  }
          }
    puts "$cnt"
    }


    Misread the question earlier sorry about that.Let me know if you think the logic is skewed.

  • kazad

    Hi Gh

    This gives all the sequential elements in the design. But I after the flops those clock nets are coming from the clock-gating cell outputs.

    Thanks

    Khandaker

     

     

  • Vishnu Chada
    Minor modification : instead of "set inst [filter_collection [all_fanout -from [get_object_name $y]/Q -endpoints_only] { is_integrated_clock_gating_cell == true }] " we should be using as the above was assigning only the clock gating cell. set inst [filter_collection [all_fanout -from [get_object_name $y]/Q -only_cells] { is_integrated_clock_gating_cell == false && is_sequential == true }]
  • kazad

    Hi Vinshu

    Thanks very much for the procedure. It really helped my need.

    Cheers

    Khandaker

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.