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Timing analysis on partitioned design in EDI

weian

After assembling the partitions into the top design, I tried to do static timing analysis over the whole design, but the timing report showed 0 slews and delays in the buffers of clock paths. It seems that the tool didn't consider the wire load while computing timing although the log file showed the RC extraction operations. In the timing analysis of each individual partition, however, the path delays looked fine. Can anyone tell me why and how to fix? Did I miss something after assembling the partitions? Thanks very much.

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  • Martinage

    It sounds like some of your clock trees are still in ideal mode.  Try running the following to
    find all clock endpoints that are not receiving a propagated clock:

    encounter 2> check_timing -check_only clock_not_propagated -verbose
    ###############################################################
    #  Generated by:      Cadence Encounter 09.13-s229_1
    #  OS:                Linux x86_64(Host ID pe-opt13)
    #  Generated on:      Wed Nov  3 17:04:26 2010
    #  Command:           check_timing -check_only clock_not_propagated -verbose
    ###############################################################
         +------------------------------------------------------+
         |                 TIMING CHECK SUMMARY                 |
         |------------------------------------------------------|
         |       Warning        |      Warning       |  Number  |
         |                      |    Description     |    of    |
         |                      |                    | Warnings |
         |----------------------+--------------------+----------|
         | clock_not_propagated | Ideal clock at pin |       10 |
         +------------------------------------------------------+
         +-----------------------------------------+
         |           TIMING CHECK DETAIL           |
         |-----------------------------------------|
         |      Pin      |         Warning         |
         |---------------+-------------------------|
         |  TR0/BR1/CK   | Ideal Clock WAVE at pin |
         |  TR1/BR1/CK   | Ideal Clock WAVE at pin |
         |    CGR/CK     | Ideal Clock WAVE at pin |
         |  BLK/BR0/CK   | Ideal Clock WAVE at pin |
         |  BLK/BR1/CK   | Ideal Clock WAVE at pin |
         |  BLK/BR11/CK  | Ideal Clock WAVE at pin |
         |  BLK/BR2/CK   | Ideal Clock WAVE at pin |
         | BLK/SPARE1/CK | Ideal Clock WAVE at pin |
         | BLK/SPARE2/CK | Ideal Clock WAVE at pin |
         |  TR2/BR1/CK   | Ideal Clock WAVE at pin |
         +-----------------------------------------+

     

    If this report does show up some ideal clocked endpoints, you likely have a set_clock_latency still set somewhere
    between the clock definition and the endpoints.  You could consider running the  reset_clock_tree_latency command.

    This will walk the specified clock trees and remove any set_clock_latency assertions that are still around.

     

Reply
  • Martinage

    It sounds like some of your clock trees are still in ideal mode.  Try running the following to
    find all clock endpoints that are not receiving a propagated clock:

    encounter 2> check_timing -check_only clock_not_propagated -verbose
    ###############################################################
    #  Generated by:      Cadence Encounter 09.13-s229_1
    #  OS:                Linux x86_64(Host ID pe-opt13)
    #  Generated on:      Wed Nov  3 17:04:26 2010
    #  Command:           check_timing -check_only clock_not_propagated -verbose
    ###############################################################
         +------------------------------------------------------+
         |                 TIMING CHECK SUMMARY                 |
         |------------------------------------------------------|
         |       Warning        |      Warning       |  Number  |
         |                      |    Description     |    of    |
         |                      |                    | Warnings |
         |----------------------+--------------------+----------|
         | clock_not_propagated | Ideal clock at pin |       10 |
         +------------------------------------------------------+
         +-----------------------------------------+
         |           TIMING CHECK DETAIL           |
         |-----------------------------------------|
         |      Pin      |         Warning         |
         |---------------+-------------------------|
         |  TR0/BR1/CK   | Ideal Clock WAVE at pin |
         |  TR1/BR1/CK   | Ideal Clock WAVE at pin |
         |    CGR/CK     | Ideal Clock WAVE at pin |
         |  BLK/BR0/CK   | Ideal Clock WAVE at pin |
         |  BLK/BR1/CK   | Ideal Clock WAVE at pin |
         |  BLK/BR11/CK  | Ideal Clock WAVE at pin |
         |  BLK/BR2/CK   | Ideal Clock WAVE at pin |
         | BLK/SPARE1/CK | Ideal Clock WAVE at pin |
         | BLK/SPARE2/CK | Ideal Clock WAVE at pin |
         |  TR2/BR1/CK   | Ideal Clock WAVE at pin |
         +-----------------------------------------+

     

    If this report does show up some ideal clocked endpoints, you likely have a set_clock_latency still set somewhere
    between the clock definition and the endpoints.  You could consider running the  reset_clock_tree_latency command.

    This will walk the specified clock trees and remove any set_clock_latency assertions that are still around.

     

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