Compatibility problem between ELC and Verilog-A

Hi all,

I want to create .lib files from elc with hspice simulator and a transistor model made with Verilog-A.

FYI, when I used a standard model (not in VerilogA), everything works properly and the .lib are generated.

When I use the model written in VerilogA, I am facing the following problem:

During the db_prepare step: the elc execution stops because when analyzing the model file and the following message appears:

"

Reading SUBCKT:NMOSFD
Reading SUBCKT:PMOSFD
[WARNING(db_prepare)] spice syntax warning: NMOSFET : no definition of the subckt
 => XM1 D G S 0 NMOSFET
[WARNING(db_prepare)] spice syntax warning: PMOSFET : no definition of the subckt
 => XM1 D G S 0 PMOSFET

SUBCKT FILE: std_cells.sp ( #size = 282 )

Reading SUBCKT:IVX2
[WARNING(db_prepare)] spice syntax warning: NMOSFET : no definition of the subckt
 => XM1 D G S 0 NMOSFET
[WARNING(db_prepare)] spice syntax warning: PMOSFET : no definition of the subckt
 => XM1 D G S 0 PMOSFET
Expanding SUBCKT:IVX2
... XM1 [NMOSFD]
... XM0 [PMOSFD]
- subckt : NMOSFET is not defined
- subckt : PMOSFET is not defined
[ERROR(db_prepare)] Cannot read the input SPICE file subckt : NMOSFET is not exist. because it has one or more syntax errors. Correct the SPICE syntax in the file and try again.
"

Please note that we never have any error when simulations this verilogA model with Hspice directly without ELC. 

Actually when ELC tries to read the model file without opening hspice, I think ELC is expecting a subckt and not a link with a VerilogA file.

Does anybody know how to do to make ELC understand this?

Or how to prevent prevent elc from checking the model before simulating with hspice during the db_prepare?

Regards,

Bastien