Conformal equivalence check fails on unused input ports

Hi,

 I am running Conformal LEC on a design written mostly in VHDL. The coding uses VHDL record types to distribute  register file information to modules. The modules take some bits of the record for configuration and other bits of the port are unused as they are for other modules.

In my RTL compiler synthesis logs, the unused bits are flagged as being unused and synthesis will keep the port in the generated Verilog netlist but nothing is attached to it (as expected). For some reason, Conformal seems to expect that the unused input has something attached to it (schematic views show that it puts 'buf' on the Golden/VHDL).

I can't find a switch to make Conformal ignore unused bits of input ports and as a result I get many non-equivalents. Most of them are probably false positives, but it becomes very hard to trace each individual failure point.

Any ideas on how to handle this would be very much appreciated.

Cheers,

Johan