How to write a sdc file for a multi-module design?

Dear all:

I want to write a sdc file including sub-module interconnection or internal connection constraints，but I encounter some problems....

For Example:

I have a Top design including  Module A and Module B. There're pin a1 and pin a2 in Module A ,and also  pin b1 and pin b2 in Module B.

1.How can I make a minimum delay constraint  on the delay from a1 to a2 in a sdc file ?

2.How can I make a minimum delay constraint on the delay from b1 to a1 in a sdc file ?

3.When I write a sdc like this :

current design Top

................

.............

current design Module A

...........................

............ 

Then,SOC Encounter encounters a fatal error and break ! 

 Please help me ~