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LEF with VIA definitions in the PORT section of each PIN

Having VIAS in the PORTS section of the PINS section for each port including the Power/Ground PINS.
Are there any advantages to having this information there? Is it useful for doing EM & IR drop analysis in SOC Encounter on the Power/Ground NETS? Or is it adding no real advantage except creating a blockage? How is
it dealt with in RC Extraction?

Originally posted in cdnusers.org by soba

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