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Re: how to do floorplanning for a flip chip

gops
Hi Kari, Thank you very much for the detailed explanation.Sorry to bother again with a few more doubts, hope you will help me again. I am aware about inline, staggered and CUP IOs. Is there any other IOs like areaIOs? how is it different from normal IOs? From your explanation I understood tat normal IOs can also be used for flip chip.am i correct? Also can you please tell me more about area IOs. how can i place it on chip. should i place them like i place the bumps?can you throw some info on them also. again thanks a lot for your help. Gops ----------------------------------------- This email was sent using SquirrelMail. "Webmail for nuts!" http://squirrelmail.org/ ______________________________________ Scanned and protected by Email scanner
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  •  Hi Gops,

     I've never used areaIOs myself, so unfortunately I can't provide any insight there. All the flip-chips I've done have used "normal" IOs - in a peripheral ring around the chip. The main difference is that areaIOs can be placed anywhere on the chip (usually under or near the bump they connect to) - they don't have to be around the outside in a padring. I believe you have rows for them so that EDI knows where they can go. For "normal" IOs, in a padring around the chip, you can choose to use rows but you don't have to. You wouldn't be able to put a "normal" IO in the middle of the chip, because these cells depend on abutment in the padring for their power rails, ESD, etc. Hope that makes sense.

    - Kari

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  •  Hi Gops,

     I've never used areaIOs myself, so unfortunately I can't provide any insight there. All the flip-chips I've done have used "normal" IOs - in a peripheral ring around the chip. The main difference is that areaIOs can be placed anywhere on the chip (usually under or near the bump they connect to) - they don't have to be around the outside in a padring. I believe you have rows for them so that EDI knows where they can go. For "normal" IOs, in a padring around the chip, you can choose to use rows but you don't have to. You wouldn't be able to put a "normal" IO in the middle of the chip, because these cells depend on abutment in the padring for their power rails, ESD, etc. Hope that makes sense.

    - Kari

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