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Physical cell positions in layout

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Hi everyone, can anyone plz tell me how can I extract physical gate positions on chip from its layout. I am very new 2 Cadence. So if very briefy u could plz write me how can i go from VHDL code 2 abstract layout (contains gate positions only). regards Touqeer


Originally posted in cdnusers.org by touqeerazam
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  • If the chip is implemented flatten, you can try those:
    -- export a def file, (file->Export->DEF), then, from the def file, the "COMPONENTS" section will give you locations for all the instances.
    -- inside Virtuso layout editor, the "Edit->Search" will let you search instances by their name, and then, select them, and query their location.
    -- If you have Virtuoso VXL, you can do schematic--layout cross probe.
    If there are physical hierarchy, you have to look into individual layout view and convert their (x y) into top level when needed.

    Tongju


    Originally posted in cdnusers.org by Tongju
Reply

  • If the chip is implemented flatten, you can try those:
    -- export a def file, (file->Export->DEF), then, from the def file, the "COMPONENTS" section will give you locations for all the instances.
    -- inside Virtuso layout editor, the "Edit->Search" will let you search instances by their name, and then, select them, and query their location.
    -- If you have Virtuoso VXL, you can do schematic--layout cross probe.
    If there are physical hierarchy, you have to look into individual layout view and convert their (x y) into top level when needed.

    Tongju


    Originally posted in cdnusers.org by Tongju
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