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Physical cell positions in layout

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Hi everyone, can anyone plz tell me how can I extract physical gate positions on chip from its layout. I am very new 2 Cadence. So if very briefy u could plz write me how can i go from VHDL code 2 abstract layout (contains gate positions only). regards Touqeer


Originally posted in cdnusers.org by touqeerazam
Parents

  • Does exporting a DEF file help? Another way is to write a skill program to print out the instance locations, like:

    cvid=geGetEditCellView
    foreach(inst cvid~>instances
    printf("%s %L\n" inst~>name inst~>xy)
    )

    Tongju


    Originally posted in cdnusers.org by Tongju
Reply

  • Does exporting a DEF file help? Another way is to write a skill program to print out the instance locations, like:

    cvid=geGetEditCellView
    foreach(inst cvid~>instances
    printf("%s %L\n" inst~>name inst~>xy)
    )

    Tongju


    Originally posted in cdnusers.org by Tongju
Children
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