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Renaming a spare module

KVBABU

 
Hi All,

Iam handling a hierarchical mixed signal design, in which i dont have spare modules either at block level  or at top level. So i have added them using "createsparemodule " command.
But, unfortunately, i have added them with same name at block level and at top level. So, i wanted to rename the spare module either at block level or at top level.

Is there any script or encounter command to this ? . I dont want to delete the existsing module and add again with new name. Because, all the exsisting spare  modules were spreaded evenly in between the exsisting logic. So , i expect that removing and adding spare cells may disctrub the exisiting scenario of my layout which is very timing critical.

PLease help in this regard .

Thanks in advance.

Regards,
K.VISWANADH BABU

Parents

  •  A general practice is to include the block name as a prefix to the spare module so you don't have conflicts at the top level. But it sounds like it's too late for you to go back now. What I would probably do is edit the verilog and def to have the new spare module/cell names. It can be tricky, depending on how complex your design is. You may want to write a perl script or something to do it. 

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  •  A general practice is to include the block name as a prefix to the spare module so you don't have conflicts at the top level. But it sounds like it's too late for you to go back now. What I would probably do is edit the verilog and def to have the new spare module/cell names. It can be tricky, depending on how complex your design is. You may want to write a perl script or something to do it. 

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