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Confliction in RTL power report using PSO method

tungthanhhoang

 I make a simple 32-bit Ripple Carry Adder in where PSO method is apply via CPF approach. The RCA consist two parts, low part 16-bit (LP_RCA) and high-part 16 bit (HP_RCA) which can be power down by external pins. I have passed all steps to make use CPF with RTL compiler. I reported power consumption for individual modes as the following example

       Instance                     Domain(Voltage)       Cells  LeakPower(nW)  DynamicPower(nW)  TotalPower(nW)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
RCA_TOP                           PD0(1.2v)                 192    18101.947              625996.442             644098.389
  inst_INREGi                      PD0(1.2v)                  66       7493.948              326447.306             333941.254
  inst_HP_RCA                    PD2_HP_RCA(1.2v)    31      7279.775              19524.280                 26804.055
  inst_OUREGi                     PD0(1.2v)                  34      3316.184             158723.864               162040.048
  CPF_ISO_HIER_INST_2     PD0(1.2v)                  16        7.301                    8295.319                  8302.620
  CPF_ISO_HIER_INST_1     PD0(1.2v)                  17        4.738                       74.394                      79.132
  inst_LP_RCA                     PD1_LP_RCA(0v)      28        0.000                         0.000                        0.000


My question is why total Dynamic power consumption of all sub-instance is not equal to the Dynamic power consummed by Top design (RCA_TOP) ?

 This problem happens even all power domains are turn OFF or ON. It seems to me that RTL LP-engine here takes into account overhead due to power switchesbut I do know how to analyze that ovehead. Is there anyway to report that overhead explicitly (even it can be easily calculated by substraction)

 Anyone has ideas ?

 /T

  • Hi Tungthanhhoang,

    power measurement can be tricky at times. Possible issue that come to mind are SPEF annotation or  clock tree power but in order to be more helpful it would be useful if you can share more details about your flow. What version of RC ? Are you reporting at RTL, netlist, SPEF annotated netlist ? Are you using VCD or TCF or defaults ? For starters I suggest you move to latest official release of 10.1.200 in downloads.cadence.com since it could certianly be an issue already addressed.

     regards,

    gh-

  •  Hi Grasshopper

    First, thank for your suggestions.Here is some detail about my flow

    - I use  Encounter Digital Implementation version 9.11 to synthesize original RCA design and assert probability and tonggle rate to design's ports including shut-off signal which is assumed ON or OFF all the time. Then, TCF file is dumped out.

     - Next, CPF version 1.1 is created. TCF and SDC files are read via CPF file. Post-synthesis netlist is extracted for power estimation. No SPEF is annotated (no place-route is performed). Report power is generated with "-mode" option, according to value of shut-off port which is set in advance.

    Since, I currently do not have version 10.1.200 in hand but I checked KPNS of version 9.11 and can not find any relevant thing.

    I am appreciate if you can let me know some hepful information.

    /T

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