Clock gating failed with Encounter

I was trying to implement my chip using the clock gating low power design feature provided in Encounter. Firstly I turned on the clock gating option in RTL compiler. The tool found all registers that are clock gating applicable and synthesized them with gated clock. Then I simulated the synthesized Verilog netlist using the same test bench for the original Verilog code. The simulation didn't consider any timing information since we were testing the logic integrity. The logic of the synthesized netlist was verified successfully.

The problem happened in place and route. After P&R, I extracted the Verilog netlist of the layout and tried to verify its logic using the same test bench (that I used for behavioral and synthesized Verilog code). The verification failed! I was surprised to see this since the P&R tool is supposed to keep the design function identical to the synthesized netlist.

I re-synthesized and re-place&route the design, but with the clock gating option turned off. This time both the synthesized and post-layout netlists passed the verification.

I tried very hard to debug the clock-gated design by disabling the clock-gating of some components. But it seems that the place&route result is unpredictable.  

Did I miss something when placing and routing the clock-gated design? Or is there special method to verify the post-layout netlist of a clock-gated design?

I'm looking forward to your comments. Thans very much.