Stats

  • Locked Locked
  • Replies 4
  • Subscribers 90
  • Views 1712
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

LVS after place&route may fail due to clock tree buffers

archive

Hello All

An LVS after place&route should compare final layout with input verilog code (i mean that verilog code used as input for place&route tool).

But during place&route, some new buffers may be added  automatically by the tool which were not in the original verilog code.

My question is how LVS should realize the new buffers?
when I run LVS by Calibre, it fails with many error messages like this:

Error: No matching ".SUBCKT" statement for "BFLVTX1" at line 1490 in file "/tmp/lvsRunDir/_decoder36.v.sp"

BFLVTX1 is a buffer used from std library.

Can anyone help me please with this issue?

Thanks,
Ali Naderi


Originally posted in cdnusers.org by Naderi
Parents Reply Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.