First Encounter pin placement/layer

Yes, without any constraints when placeDesign runs it places the IO pins such that they are as close as possible to the instance(s) each pin is connected to. I like to visually assess this using "selectIOPin *"- if the tool has done a good job, you should see straight flight lines connecting from each IO pin to the nearest instance each is connected to.

From there, you can constraint pin placement in several ways. There's a pretty good write up on this subject in the SoC-Encounter User's Guide, described in most depth in the Partitioning section under the "Assigning Pins" section. It's worth noting explictly that the constraints available for partition pins also apply to IO pins (the general convention is that the -cell option should be used with the top cell name specified as the cell). If you're you're unsure what the top cell name is you can use "dbGet top.name".

Dropping down a level in detail to your specific request of "Can FE place IO pins along a given edge, maintaining the order while optimizing the pin location for easier route access?". I've worked through this scenario in the past with mixed results honestly. Perhaps if I describe the mechanisms used to constrain the tool to do what you're asking for you could try it on your design to see if it aligns with your needs?

createPinGroup myGroup -cell testcase -pin {out1 out2}
->order is important here
->do not specify -optimizeOrder if you want the order maintained as specified

createPinGuide -edge 1 -pinGroup myGroup -cell testcase -layer {2 3}
->Edges start at "0" with the lower left corner and increases by 1 for each edge clockwise
->Visually, in the floorplan view after createPinGuide you should see small white guides around the edges after this step
->By default, the system disallows pins on M1. If you require M1 pins, please post back for further guidance.

From there, you should be able to "placeDesign" and have the tool place the standard cells and IO pins.

I should mention that I've seen some quality of results issues while attempting to constrain the tool in this specific manner (order maintained while giving the tool flexibility to determine locations). Pin assignment with groups and guides sometimes likes to stack up the pins at the user-defined minimum spacing rather than truly optimizing their locations when the order is required to be maintained.

Sometimes, it is easier to write a script using "editPin" to place the pins in the order you like with a user-determined gap between each pin. editPin is smart enough to dodge around power preroutes and such so I thought I'd mention that as an alternative.

Great questions- keep 'em coming!

Hope this helps,
Bob

Yes, without any constraints when placeDesign runs it places the IO pins such that they are as close as possible to the instance(s) each pin is connected to. I like to visually assess this using "selectIOPin *"- if the tool has done a good job, you should see straight flight lines connecting from each IO pin to the nearest instance each is connected to.

From there, you can constraint pin placement in several ways. There's a pretty good write up on this subject in the SoC-Encounter User's Guide, described in most depth in the Partitioning section under the "Assigning Pins" section. It's worth noting explictly that the constraints available for partition pins also apply to IO pins (the general convention is that the -cell option should be used with the top cell name specified as the cell). If you're you're unsure what the top cell name is you can use "dbGet top.name".

Dropping down a level in detail to your specific request of "Can FE place IO pins along a given edge, maintaining the order while optimizing the pin location for easier route access?". I've worked through this scenario in the past with mixed results honestly. Perhaps if I describe the mechanisms used to constrain the tool to do what you're asking for you could try it on your design to see if it aligns with your needs?

createPinGroup myGroup -cell testcase -pin {out1 out2}
->order is important here
->do not specify -optimizeOrder if you want the order maintained as specified

createPinGuide -edge 1 -pinGroup myGroup -cell testcase -layer {2 3}
->Edges start at "0" with the lower left corner and increases by 1 for each edge clockwise
->Visually, in the floorplan view after createPinGuide you should see small white guides around the edges after this step
->By default, the system disallows pins on M1. If you require M1 pins, please post back for further guidance.

From there, you should be able to "placeDesign" and have the tool place the standard cells and IO pins.

I should mention that I've seen some quality of results issues while attempting to constrain the tool in this specific manner (order maintained while giving the tool flexibility to determine locations). Pin assignment with groups and guides sometimes likes to stack up the pins at the user-defined minimum spacing rather than truly optimizing their locations when the order is required to be maintained.

Sometimes, it is easier to write a script using "editPin" to place the pins in the order you like with a user-determined gap between each pin. editPin is smart enough to dodge around power preroutes and such so I thought I'd mention that as an alternative.

Great questions- keep 'em coming!

Hope this helps,
Bob