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  3. First Encounter pin placement/layer

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First Encounter pin placement/layer

archive
archive over 17 years ago

Hi there,

can anyone tell me how to make Encounter place pins on restricted layers, for example on metals 1 & 2 only. Ultimately i'd like my pins placed on a given boundary edge & in a pre-determined order.

Thanks

Stu

p.s I'm actually an alaog layout guy using Encounter (for the first time) to place and route a large digital block in an analog chip. Apologies for the simple Q's, there will be more.


Originally posted in cdnusers.org by sreilly
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  • archive
    archive over 17 years ago

    Hi Bob, agian thanks for your info. I'd just typed a long winded reply and lost connection before i got to post it, very annoying!!!

    Anyway the short reply was that i need to try a few test cases of constraining the pin placement and compare it no constraint placement. My gut feeling is that its more efficient to let the tool place the pins and then i can deal with the connection at the level above, given that its an analog chip and i'll be custom routing at top-level anyway.

    Do you mind another couple of Q's? (should i start another thread for these, i don't want to clog up the forum)

    1) How do you tell FE (First Encounter) that its ok to stack vias and contacts, it appears not to be at present?

    2) Can i get FE to indicate what % of area of my floorplan is being utilised once i've placed my logic? At present i'm setting my floorplan dimensions BEFORE i place the logic. Is this standard practice as this assume i have reasonable feel for the block size before i place any blocks or do any hook-up?

    Cheers

    Stu


    Originally posted in cdnusers.org by sreilly
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  • archive
    archive over 17 years ago

    Hi Bob, agian thanks for your info. I'd just typed a long winded reply and lost connection before i got to post it, very annoying!!!

    Anyway the short reply was that i need to try a few test cases of constraining the pin placement and compare it no constraint placement. My gut feeling is that its more efficient to let the tool place the pins and then i can deal with the connection at the level above, given that its an analog chip and i'll be custom routing at top-level anyway.

    Do you mind another couple of Q's? (should i start another thread for these, i don't want to clog up the forum)

    1) How do you tell FE (First Encounter) that its ok to stack vias and contacts, it appears not to be at present?

    2) Can i get FE to indicate what % of area of my floorplan is being utilised once i've placed my logic? At present i'm setting my floorplan dimensions BEFORE i place the logic. Is this standard practice as this assume i have reasonable feel for the block size before i place any blocks or do any hook-up?

    Cheers

    Stu


    Originally posted in cdnusers.org by sreilly
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