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First Encounter pin placement/layer

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Hi there,

can anyone tell me how to make Encounter place pins on restricted layers, for example on metals 1 & 2 only. Ultimately i'd like my pins placed on a given boundary edge & in a pre-determined order.

Thanks

Stu

p.s I'm actually an alaog layout guy using Encounter (for the first time) to place and route a large digital block in an analog chip. Apologies for the simple Q's, there will be more.


Originally posted in cdnusers.org by sreilly
Parents

  • Hi Stu,

    You're welcome.

    1) For via stacking, the tool should determine this automatically from rules present in the technology LEF. Either your technology LEF is a crude one (and lacks the details to enable the tool to stack vias) or there's something going wrong. It may also depend on whether you're talking about signal routes or power routes in terms of the needed action on your part to encourage stacking. Maybe you could provide some additional detail on your scenario?

    2) For density you probably want to use a command like "queryPlaceDensity" to assess what the standard cell density is after floorplanning the design. This TCL command is equivalent to clicking the circular green icon with a percent sign on the main FE GUI. The difference between queryPlaceDensity and the density # you target when initializing the floorplan size is that nuances like placement blockages, power preroutes that preclude standard cell placement, placement density screens and the like aren't taken into account when determining the initial size of the design as a percentage.

    It's probably best to post new topics individually so that people can see if there's a subject line they're interested in, but no biggie. Either way.

    Thanks,
    Bob


    Originally posted in cdnusers.org by BobD
Reply

  • Hi Stu,

    You're welcome.

    1) For via stacking, the tool should determine this automatically from rules present in the technology LEF. Either your technology LEF is a crude one (and lacks the details to enable the tool to stack vias) or there's something going wrong. It may also depend on whether you're talking about signal routes or power routes in terms of the needed action on your part to encourage stacking. Maybe you could provide some additional detail on your scenario?

    2) For density you probably want to use a command like "queryPlaceDensity" to assess what the standard cell density is after floorplanning the design. This TCL command is equivalent to clicking the circular green icon with a percent sign on the main FE GUI. The difference between queryPlaceDensity and the density # you target when initializing the floorplan size is that nuances like placement blockages, power preroutes that preclude standard cell placement, placement density screens and the like aren't taken into account when determining the initial size of the design as a percentage.

    It's probably best to post new topics individually so that people can see if there's a subject line they're interested in, but no biggie. Either way.

    Thanks,
    Bob


    Originally posted in cdnusers.org by BobD
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