Stats

  • Locked Locked
  • Replies 8
  • Subscribers 90
  • Views 21338
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

No matching .SUBCKT statement error in LVS check

archive

Hello All I am using Calibre-LVS for LVS check between final layout and verilog code both are generated by Cadence-Encounter v4.1. The output log file is enclosed. The LVS does not compare two files because of some errors like: Error: No matching ".SUBCKT" statement for "BFSVTX10" at line 43459 in file "/tmp/lvsRunDir/_decoder36.v.sp" Error: No matching ".SUBCKT" statement for "BFSVTX10" at line 43460 in file "/tmp/lvsRunDir/_decoder36.v.sp" BFSVTX10 is a standard lib given in STM cmos90nm lib. I appreciate your comment to solve this issue. Thanks, Ali


Originally posted in cdnusers.org by Naderi
Parents

  • Hello Kari,

    Thanks for your reply.
    There is a verilog translator integrated into the Calibre-LVS. I entered a verilog file (for netlist ) and a layout (a GDS file was imported to vituoso layout) as two inputs for the LVS. Hence I didn't use v2lvs. But if it is not a safe method please let me know the correct syntax.
    Also I didn't mention the std cells. I think this is the step I missed. How should I introduced them to the design? at starting point of the LVS check I see some warnings like this:

    "Warning: no module declaration for module CTBUFLVTX12_0 first encountered in module decoder36"

    CTBUFLVTX12_0 is std buffer from cmos90nm library.
    decoder36 is my top cell name.

    Thanks,
    Ali


    Originally posted in cdnusers.org by Naderi
Reply

  • Hello Kari,

    Thanks for your reply.
    There is a verilog translator integrated into the Calibre-LVS. I entered a verilog file (for netlist ) and a layout (a GDS file was imported to vituoso layout) as two inputs for the LVS. Hence I didn't use v2lvs. But if it is not a safe method please let me know the correct syntax.
    Also I didn't mention the std cells. I think this is the step I missed. How should I introduced them to the design? at starting point of the LVS check I see some warnings like this:

    "Warning: no module declaration for module CTBUFLVTX12_0 first encountered in module decoder36"

    CTBUFLVTX12_0 is std buffer from cmos90nm library.
    decoder36 is my top cell name.

    Thanks,
    Ali


    Originally posted in cdnusers.org by Naderi
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.