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clock tree file creation for multiple PLL scenario

Hi all,

The clockscheme in my design is as shown in the jpeg.

Can anyone please help me with the generation of the clock tree file for this clock scheme ( a sample ctstch file for the scheme will be good enough).

Kindly give me some idea of giving the MaxDelay,MinDelay,MaxSkew values for the clock with respect to the jitter and Tlock specified in the diagram.

thank you very much for the time and effort.

thanks

Gops

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Kari over 14 years ago

Encounter can generate the .ctstch file for you. Start with that, then adjust as needed. Jitter is usually considered when coming up with the set_clock_uncertainty constraint in the SDC file.
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Kari over 14 years ago

Encounter can generate the .ctstch file for you. Start with that, then adjust as needed. Jitter is usually considered when coming up with the set_clock_uncertainty constraint in the SDC file.
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