We try to fabricate our chip with MOSIS and submit our design. But
there is an error during DRC ERROR: no CHIPEDGE seen.
We ask help for MOSIS technical support and they say:
"CHIPEDGE is something you can teach Encounter to draw for you",
it is a special Encounter instruction sequence. You will have to search
your Encounter documentation to find it. Search on keywords such as
"drawing a bounding box polygon" or "chamfer" or even "CHIPEDGE" might
give you a hit. With that sequence you can force Encounter to draw the
CHIPEDGE polygon directly".
We search the whole encounter document but cannot get a hit. If anyone know something like this, please help us.
I've always used Virtuoso to design the CHIPEDGE. Usually there is a design kit from the foundry that contains the pieces you need to put it together.
I was wondering if you could provide more details regarding adding the GUARDRING, CHIPEDGE, GUARDEDGE, LOGOBND, etc. I have found some cells in Virtuoso and am also brand new to the tool. Is it fairly easy to modify the chipedge for my die size? Also, do you have any references or advice?
Thank you Kari,
I'm starting by using the crackstop cell that is included by the foundry, but I'm having all types of issues with it. Apparently it is a P-cell, (parameterized cell), but I'm not sure how to modify the properties of it for the dimensions of my die.
My current process is this:
setup cds.lib and open virtuoso, but then I get an error from virtuoso saying
"There is a conflict in techfile graph (cmos32). Look at the techfile reported error message in CIW. Correct techfile conflict before proceeding" Then in the CIW window I get thjese messages:
*WARNING* (TECH-2000178): A Purpose Number conflict has been detected in the technology hierarchy. It is caused by the following list of purposes: cmos32/cont0 (#40), cdsDefTechLib/P40 (#40);
*WARNING* Technology database conflict: There are purpose numbers which conflict in the incremental techlibs
*WARNING* (TECH-2000050): Unable to set references on tech because conflicts would results in tech cmos32
So in my cmos32soi library (specified in my cds.lib), there is a tech.db. Also it appears virtuoso loads the default tech.lib from cdsDefTechLib, but for some reason this is causing a problem that I can't figure out.
If I press okay on the error message window that pops up when virtuoso starts, my procedure is as follows for creating my own crackstop:
I create a new library (Tools-->Library Manager)
In the library list I see the following:
US_8ths, analLib, basic, cdsDefTechLib, cmos32, sample, sbaLib
I then click on File--> New Library, I specify a directory name called mynewlibrary, attach to an existing technology library, set the technology library as cmos32
Then I click on the cmos32 library, highlight the crackstop cell, and create a copy to my 'mynewlibrary'. When I then try and open up the layout view (which is the only view I have), I am unable to edit any of the parameters, I don't know how. Sometimes I am able to select the crackstop, othertimes not, but I am always able to see it.
I was wondering if you have any advice or anything you notice I am doing wrong?
Thank you very much