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spare logic is not tied up/down properly after ECO route

In my ECO step, a number of logic gates are freed up and become spare gates. They should be connected to VDD or GND selectively. What command should I use? The large majority are grounded, but a few are tied high.

Note:

I don't have tieHi or tieLo cells in my library; I want to hook up directly.

When I query the pin, the net shown is "NIL".

J2mh over 14 years ago

Hi,

If your library have an inversor cell then you can create tiehigh and tielow cells, easily.

Regards.
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