From Verilog to layout - Flow problems

 Hi,

sorry for this long post but I'm having some issues with a flow that ideally would start from a Verilog description and end with a layout. I try to describe shortly what I do and where I find problems.

1) Describe the design in Verilog: create 2 different cells (controller and counter). So, for each cell I have a Verilog description and a symbol

2a) Simulate: I can create a schematic, connect the symbols of the two cells, connect a testbench (Verilog) and simulate.

2b) Now, I want to do the same thing BUT instead of a schematic I want to create a top cell (Pixel) that contains controller and counter. Now I have the symbol and the verilog description of Pixel. I connect Pixel to testbench and simulate.

3) With RTL compiler I can synthesize the top-level Pixel producing a pixel_synthesized.v netlist. Question: how do I do simulations for this?

4) I can P&R in Encounter the pixel_synthesized.v netlist and produce a layout and a post-layout netlist called pixel_routed.v (to create this netlist I use saveNetlist pixel_routed.v -includePowerGround).

5) I can move everything back in Virtuoso: I have the layout of the Pixel. I use Import->Verilog to import the post-layout netlist to be able to perform LVS. This operation creates for _every_ cell a schematic view (so, now, I have Verilog, Schematic and Symbol).

Many problems here:

- the generated schematic has VDD! and GND! pins, but I want them to be called VDD and GND. In the Import form I set correctly the names, but still the problem is there. I can anyway change manually the name of the pins (both in schematic and symbol), but it seems a waste of time.

- the schematic has the pins VDD and GND while the Verilog doesn't. The symbol is now automatically modified to have VDD and GND pins. This mess up the previous test I made (the symbol is changed) but, more important, now those test don't run anymore! I'm using config view to run the simulations, and if I select the schematic view in the form everything works fine, but if I select the Verilog view (as it was in origin) the compiler gives me an error. NB: if I select the Verilog view for the top cell (Pixel) the hierarchy editor says that it cannot find the sub-modules contained! Instead if I select the schematic view, everything works fine. 

I tried to solve this using the `include directive in the top-level (Pixel) referencing the verilog description of the two sub-blocks, but again the compiler says it cannot open the files:

Thanks for any help, I hope it is clear what is happening, if not ask for clarifications please! :)

Francesco