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SDF Errors

tswong

We are performing postlayout simulation for a digital design which adopts TSMC 65nm standard cell library. During SDF back annotation by Verilog-XL 8.2, there are many SDFA errors, "Failed to find SETUP timingcheck" and "Failed to find HOLD timingcheck". But the simulation is still passed. Is it caused by mismatch Verilog model of the standard cells? or by improper EDA tools? Is it important?

Thanks!

Parents

  •  It sounds like the timing checks in your verilog model do not match those in your .lib files. The SDF is generated based on the timing in the .lib file. During back-annotation, it tries to match the SDF timing to a timingcheck in the verilog model. What appears to be happening above is that during back-annotation, it can't find the setup and hold timing checks in your verilog model.

    If this is what's happening, it is important, because even though the simulation is passing, it may be passing without performing setup and hold timing checks.

Reply

  •  It sounds like the timing checks in your verilog model do not match those in your .lib files. The SDF is generated based on the timing in the .lib file. During back-annotation, it tries to match the SDF timing to a timingcheck in the verilog model. What appears to be happening above is that during back-annotation, it can't find the setup and hold timing checks in your verilog model.

    If this is what's happening, it is important, because even though the simulation is passing, it may be passing without performing setup and hold timing checks.

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