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SDF Errors

tswong

We are performing postlayout simulation for a digital design which adopts TSMC 65nm standard cell library. During SDF back annotation by Verilog-XL 8.2, there are many SDFA errors, "Failed to find SETUP timingcheck" and "Failed to find HOLD timingcheck". But the simulation is still passed. Is it caused by mismatch Verilog model of the standard cells? or by improper EDA tools? Is it important?

Thanks!

Parents

  • Check in you ncelab/irun log file for: 

        Annotating SDF timing data:
            Compiled SDF file:     Your_Design.sdf.X
            Log file:              logs/design.log
            Backannotation scope:  tb.dut
            Configuration file:    
            MTM control:           MINIMUM
            Scale factors:         1:1:1
            Scale type:            
        Annotation completed with 0 Errors and 16 Warnings

    Do you have any Errors ? 

     

Reply

  • Check in you ncelab/irun log file for: 

        Annotating SDF timing data:
            Compiled SDF file:     Your_Design.sdf.X
            Log file:              logs/design.log
            Backannotation scope:  tb.dut
            Configuration file:    
            MTM control:           MINIMUM
            Scale factors:         1:1:1
            Scale type:            
        Annotation completed with 0 Errors and 16 Warnings

    Do you have any Errors ? 

     

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