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SDF Errors

tswong

We are performing postlayout simulation for a digital design which adopts TSMC 65nm standard cell library. During SDF back annotation by Verilog-XL 8.2, there are many SDFA errors, "Failed to find SETUP timingcheck" and "Failed to find HOLD timingcheck". But the simulation is still passed. Is it caused by mismatch Verilog model of the standard cells? or by improper EDA tools? Is it important?

Thanks!

Parents

  • The verilog models are not generated by synthesis or modified by the router. I think you might be referring to instantiations of gates in a netlist (which are synthesized and affected by the router). 

    The verilog models I was referring to are the verilog library of the standard cells. These define the funtions and behaviors of the gates instantiated in the netlist. They are used by ncverilog to simulate the instances in the netlist.

    What you need to do is look at the timingcheck section for a flop in the SDF file and compare it to the timingcheck section in the verilog model of the same cell. For each timing check in the SDF, there should be a matching timing check in the verilog model. This matching timing check in the verilog model is what the SDF back-annotates to. When there is a timing check in the SDF that does not have a matching timing check in the verilog model, there is nothing for that SDF timing check to back-annotate to. That is when you get an error or warning like the ones you are seeing.

Reply

  • The verilog models are not generated by synthesis or modified by the router. I think you might be referring to instantiations of gates in a netlist (which are synthesized and affected by the router). 

    The verilog models I was referring to are the verilog library of the standard cells. These define the funtions and behaviors of the gates instantiated in the netlist. They are used by ncverilog to simulate the instances in the netlist.

    What you need to do is look at the timingcheck section for a flop in the SDF file and compare it to the timingcheck section in the verilog model of the same cell. For each timing check in the SDF, there should be a matching timing check in the verilog model. This matching timing check in the verilog model is what the SDF back-annotates to. When there is a timing check in the SDF that does not have a matching timing check in the verilog model, there is nothing for that SDF timing check to back-annotate to. That is when you get an error or warning like the ones you are seeing.

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