We are performing postlayout simulation for a digital design which adopts TSMC 65nm standard cell library. During SDF back annotation by Verilog-XL 8.2, there are many SDFA errors, "Failed to find SETUP timingcheck" and "Failed to find HOLD timingcheck". But the simulation is still passed. Is it caused by mismatch Verilog model of the standard cells? or by improper EDA tools? Is it important?
I have a situation similar to that of this thread. Some of our cells have sdf annotations unspecified in the verilog (giving a elaboration warning), but I also have missing sdf annotations requested in the verilog (thus leaving the default check values of 1 ns). I looked a bit but I'm still stuck.
Basically, if I use my hdl compiler to generate a sdf without RC, I get everything I need, and the elaborator does not complain. In this sdf, I have 3 setup checks, 3 hold checks and 3 width checks.
When I use encounter, I get 3 width checks, 2 setuphold checks and 1 recrem check. From the pin names of the recrem I'm pretty sure this sdf annotation replaced the missing setup/hold pair that I'm looking for. I tried telling encounter to use version 2.1 sdf with the -remashold switch, and got one more hold, related to a recovery (which is of course not in the verilog specify block).
Any ideas on which end to work? Add/modify the specify fields in the verilog, or work out how to write out the necessary fields in the sdf? I'd like to give more details, but I'm not sure what could be useful at this point.