ELC library charachterization: db_prepare, gate file

 Hello,

I am trying to characterize a bidirectional IO pad with a modified gate file using ELC 9.13. I don't get it run as described in the UG (gate file section, example BIO). I already had a look at the App Note, but still I have a few questions.

If I do it as described in UG, I'll get "unknown node names" for the internal nets ( P & N in example).
But both of my internal nets (N_30, N_40) are existing in the subcircuit Spice netlist.
 
So, I add my nets N_30 and N_40 as ports in the subckt header of the spice netlist, is that right?
Do I have to do this?

from

 subckt pio64x GND! EN PAD VDD! VDDIO DI DO

to

  subckt pio64x GND! EN PAD VDD! VDDIO DI DO N_30 N_40

Now, if I run db_prepare -f, I get a "database mismatch".
Only, if I add output port declarations for N_30 and N_40 in my gate file, db_prepare will succeed.

----------------------------- snip----- gate file ----------------

 //    =================
//     PORT DEFINITION
//    =================
    INPUT DI ( DI );
    INPUT EN ( EN );
    OUTPUT DO ( DO );
    OUTPUT N_30 ( N_30 );
    OUTPUT N_40 (  N_40 );
    INOUT PAD ( PAD , N_40, N_30 );

----------------------------- snap----- gate file ----------------

But is that the right flow, because nothing is written in the UG and AppNote about spice netlist modification.

Thanks for your help,
Scudex