Assura BlackBox LVS issue + un-named Pins in imported layout in virtuoso

I have been using Encounter Digital Implementation system v 9.1 for generating automated digital layout from verilog description. Up till now I have synthesized a 6-bit counter, done automated PnR and CTS etc. I have checked the layout by verify -connectivity, verify – geometry and verify antenna. The design is clean but I want to integrate my digital with the analog blocks in virtuoso. So I streamed out the counter’s layout as gds. When I import gds of this counter to virtuoso, I am facing two issues:

1)  In the imported layout of my counter in virtuoso, Pins are placed in metal 2 the same way as in Encounter but there is no net information, i.e. I cannot identify which pin is carrying which signal! How do I bring net/signal information on the pins including power and gnd pins? Do I have to manually name all the pins? This will be a great problem for large designs carrying hundreds of nets.

2) I have been able to perform Assura DRC; it’s clean J but when I try to do Assura LVS as black box, after including a file in ‘Modify avParameters’ in which I have mentioned all my standard cells as blackBox in both sch and lay, LVS just fail!! The error is:

The schematic was never extracted or is not current in schematic editor. The last schematic property is missing.

I have checked and saved the schematic several times but the problem remains. Please help me out. My Assura’s subversion is 4.1_USR2. My library vendor has provided me LEF file of the standard cells and I have imported LEF through virtuoso and produced abstract views of all the standard cells.

 Have a great day and good luck.

 Moaaz, IAT