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ELC Simulation failed with status 512

rangha

 I am trying to create a standard cell library with transistor level model written in verilog A. 

I am getting the following output 

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
               Simulation Summary               
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
-------------+-------------+----------+--------------+-----------
-------------+-------------+----------+------------+-----------+------------
   DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
-------------+-------------+----------+------------+-----------+------------
INVX1          typical       D0000     SIMULATE     FAIL        all_cells_tfet
INVX1          typical       D0001     SIMULATE     FAIL        all_cells_tfet
-------------+-------------+----------+------------+----------

 

When I checked the log file for error. I see " Simulation failed with status 512".

What does this error mean? Can anyone help me fix this issue?

 

Thanks

 Rangha

 

Parents

  •  Hello,

    I have the same problem when I try to characterize an inverter based on umc 65nmll technology. I use different configuration, setup and command file and I always result with "Simulation failed with the status 512" .

    Can you please help me?

    Below are the command output, and besides  the elc configuration, command and setup files.

     Part of command output:

    . . .

    ================================
      stimulus generation  summary 
    ================================
    Name            #MOS    #DVEC   #RVEC
    ----------------------------------------
    INVX1           2       2       0
    ----------------------------------------
                            2       0
     Reading setup file : /home/simop/cadence/umc65ll_lib/ELC/setup.std
     -        INVX1 (CELL) -      typical - 2012-07-13 12:25:26 (2012-07-13 09:25:26 GMT)

    elc>   db_gate


    ==============================
          DESIGN : INVX1
    ==============================
    DESIGN ( INVX1 );
    //      =================
    //       PORT DEFINITION
    //      =================
            INPUT A ( A );
            OUTPUT Y ( Y );
            SUPPLY0 GND ( GND );
            SUPPLY1 VDD ( VDD );
    //      ===========
    //       INSTANCES
    //      ===========
            NOT ( Y, A );
    END_OF_DESIGN;


    elc>  db_spice -s spectre -keep_log -keep_wave


       DESIGN        PROCESS       #ID         STATUS     IPDB
    -------------+-------------+----------+--------------+-----------
    INVX1          typical       D0000         SIMULATE     ceid_vlsiLab_umc65ll_stdCells
    INVX1          typical       D0001         SIMULATE     ceid_vlsiLab_umc65ll_stdCells
    ============|=============|=============|==========|==============
    INVX1          typical       2          2            ceid_vlsiLab_umc65ll_stdCells
    --*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*
     2012-07-13 12:25:26 (2012-07-13 09:25:26 GMT) : Vectors Launched 1/2
    --*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*
     2012-07-13 12:25:26 (2012-07-13 09:25:26 GMT) : Vectors Launched 2/2
    -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
                   Simulation Summary               
    -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
    -------------+-------------+----------+--------------+-----------
    -------------+-------------+----------+------------+-----------+------------
       DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
    -------------+-------------+----------+------------+-----------+------------
    INVX1          typical       D0000     SIMULATE     FAIL        ceid_vlsiLab_umc65ll_stdCells
    INVX1          typical       D0001     SIMULATE     FAIL        ceid_vlsiLab_umc65ll_stdCells
    -------------+-------------+----------+------------+----------

    . . .


    elccfg:

    #Specify the environment variable settings.
    EC_SIM_USE_LSF=1;
    EC_SIM_LSF_CMD=" ";
    EC_SIM_LSF_PARALLEL=10;
    EC_SIM_TYPE="spectre";
    EC_SIM_NAME="spectre";
    EC_SPICE_SIMPLIFY=1;
    EC_CHAR="ECSM-TIMING ECSM-POWER";
     
    #Specify the characterization inputs.
     
    SUBCKT="ceid_allStdCells_ELC.scs";
    MODEL="ll_rvt.scs";
    DESIGNS="INVX1";
    SETUP="/home/simop/cadence/umc65ll_lib/ELC/setup.std";
    PROCESS="typical";

     

    Command file:

    db_open ceid_vlsiLab_umc65ll_stdCells
     db_prepare -f
     db_gate
    db_spice -s spectre -keep_log -keep_wave
    db_wave -d INVX1 -p typical -id D0000
     db_output -lib out.lib -process typical -state
     db_close
     exit
     

     

     Setup file:

     Process typical {

            voltage     = 1.2   ; // as voltage

    temp        = 25    ; /* as temperature */

    Vtn     = 0.208 ;

    Vtp     = 0.208 ;

    } ;

     

    Process best {

            voltage     = 1.32   ; // as voltage

    temp        = 0    ; /* as temperature */

    Vtn     = 0.272  ;

    Vtp     = 0.272  ;

    } ;

     

    Process worst {

            voltage     = 1.08   ; // as voltage

    temp        = 125    ; /* as temperature */

    Vtn = 0.192  ;

    Vtp = 0.192  ;

    } ;

     

    Signal  std_cell {

    unit  = REL  ;          // relative value

    Vh    = 1.0  1.0 ;      // 100% rise/fall

    Vl    = 0.0  0.0 ;

    Vth   = 0.5  0.5 ;     // 50% rise/fall

    Vsh   = 0.8  0.8 ;

    Vsl   = 0.2  0.2 ;

    tsmax = 1.0n     ;     // maximum output slew rate

    } ;


    Simulation std_cell {

    transient    = 1.0n 100n  10p  ;

    bisec        = 6.0n 6.0n 10ps ;  // binary search

    resistance   = 10MEG;

    } ;

    Index   X1 {

    BSlew  = 0.0385N 0.5360N 2.0000N ;  // optional for binary search

    slew   = 0.0385N 0.0744N 0.1440N 0.2780N 0.5360N 1.0360N 2.0000N ;
    load   = 0.00082P 0.00330P 0.00842P 0.01848P 0.03861P 0.07870P 0.18975P ;
    } ;

     

    Index   XL {

    load   = 0.00041P 0.00165P 0.00421P 0.00924P 0.01930P 0.03935P 0.09488P ;
    } ;

     

    Index   X2 {

    load   = 0.00165P 0.00660P 0.01683P 0.03696P 0.07722P 0.15741P 0.37950P ;
    } ;

     

    Index   X3 {

    load   = 0.00248P 0.00990P 0.02524P 0.05544P 0.11583P 0.23612P 0.56925P ;
    } ;

    Index   X4 {

    load   = 0.00330P 0.01320P 0.03366P 0.07392P 0.15444P 0.31482P 0.75900P ;
    } ;

     

    Index   X6 {

    load   = 0.00495P 0.01980P 0.05049P 0.11088P 0.23166P 0.47223P 1.13850P ;
    } ;

    Index   X8 {

    load   = 0.00660P 0.02640P 0.06732P 0.14784P 0.30888P 0.62964P 1.51800P ;
    } ;

    Index   X12 {

    load   = 0.00990P 0.03960P 0.10098P 0.22176P 0.46332P 0.94446P 2.27700P ;
    } ;

    Index   X16 {

    load   = 0.01320P 0.05280P 0.13464P 0.29568P 0.61776P 1.25928P 3.03600P ;
    } ;

    Index   X20 {

    load   = 0.01650P 0.06600P 0.16830P 0.36960P 0.77220P 1.57410P 3.79500P ;
    } ;

     

    Index   CK_SLW {

    bslew   = 0.0385N 0.5360N 1.0360N ;

    } ;

     

    Group   CK_SLW {

    PIN = *.CK ;

    } ;

     

    Group   XL {

    CELL = *XL ;

    } ;

    Group   X1 {

    CELL = *X1 ;

    } ;

    Group   X2 {

    CELL = *X2 ;

    } ;

    Group   X3 {

    CELL = *X3 ;

    } ;

    Group   X4 {

    CELL = *X4 ;

    } ;

    Group   X6 {

    CELL = *X6 ;

    } ;

    Group   X8 {

    CELL = *X8 ;

    } ;

    Group   X12 {

    CELL = *X12 ;

    } ;

    Group   X16 {

    CELL = *X16 ;

    }

    } ;

    Group   X20 {

    CELL = *X20 ;

    } ;

     

    Margin   m0 {

    setup   = 1.0 0.0 ;

    hold    = 1.0 0.0 ;

    release = 1.0 0.0 ;

    removal = 1.0 0.0 ;

    recovery = 1.0 0.0 ;

    width   = 1.0 0.0 ;

    delay   = 1.0 0.0 ;

    power   = 1.0 0.0 ;

    cap     = 1.0 0.0 ;

    } ;

     

    Nominal  n0 {

    delay   = 0.5 0.5 ; // as rise fall

    power   = 0.5 0.5 ;

    cap     = 0.5 0.5 ;

    } ;

     

    // Control Section

    //

     

    set process (best,typical,worst) {

    simulation = std_cell ;

    index      = X1    ;

    signal     = std_cell  ;

    margin     = m0    ;

    nominal    = n0    ;

    } ;

     

    set index  (best,typical,worst) {

            Group(XL)  = XL  ;

    //      Group(X1)  = X1  ;

            Group(X2)  = X2  ;

            Group(X3)  = X3  ;

            Group(X4)  = X4  ;

            Group(X6)  = X6  ;

            Group(X8)  = X8  ;

            Group(X12) = X12 ;

            Group(X16) = X16 ;

            Group(X20) = X20 ;

    Group(CK_SLW) = CK_SLW ;

    } ;


    Thanks in advance,

    Thodoros

Reply

  •  Hello,

    I have the same problem when I try to characterize an inverter based on umc 65nmll technology. I use different configuration, setup and command file and I always result with "Simulation failed with the status 512" .

    Can you please help me?

    Below are the command output, and besides  the elc configuration, command and setup files.

     Part of command output:

    . . .

    ================================
      stimulus generation  summary 
    ================================
    Name            #MOS    #DVEC   #RVEC
    ----------------------------------------
    INVX1           2       2       0
    ----------------------------------------
                            2       0
     Reading setup file : /home/simop/cadence/umc65ll_lib/ELC/setup.std
     -        INVX1 (CELL) -      typical - 2012-07-13 12:25:26 (2012-07-13 09:25:26 GMT)

    elc>   db_gate


    ==============================
          DESIGN : INVX1
    ==============================
    DESIGN ( INVX1 );
    //      =================
    //       PORT DEFINITION
    //      =================
            INPUT A ( A );
            OUTPUT Y ( Y );
            SUPPLY0 GND ( GND );
            SUPPLY1 VDD ( VDD );
    //      ===========
    //       INSTANCES
    //      ===========
            NOT ( Y, A );
    END_OF_DESIGN;


    elc>  db_spice -s spectre -keep_log -keep_wave


       DESIGN        PROCESS       #ID         STATUS     IPDB
    -------------+-------------+----------+--------------+-----------
    INVX1          typical       D0000         SIMULATE     ceid_vlsiLab_umc65ll_stdCells
    INVX1          typical       D0001         SIMULATE     ceid_vlsiLab_umc65ll_stdCells
    ============|=============|=============|==========|==============
    INVX1          typical       2          2            ceid_vlsiLab_umc65ll_stdCells
    --*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*
     2012-07-13 12:25:26 (2012-07-13 09:25:26 GMT) : Vectors Launched 1/2
    --*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*
     2012-07-13 12:25:26 (2012-07-13 09:25:26 GMT) : Vectors Launched 2/2
    -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
                   Simulation Summary               
    -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
    -------------+-------------+----------+--------------+-----------
    -------------+-------------+----------+------------+-----------+------------
       DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
    -------------+-------------+----------+------------+-----------+------------
    INVX1          typical       D0000     SIMULATE     FAIL        ceid_vlsiLab_umc65ll_stdCells
    INVX1          typical       D0001     SIMULATE     FAIL        ceid_vlsiLab_umc65ll_stdCells
    -------------+-------------+----------+------------+----------

    . . .


    elccfg:

    #Specify the environment variable settings.
    EC_SIM_USE_LSF=1;
    EC_SIM_LSF_CMD=" ";
    EC_SIM_LSF_PARALLEL=10;
    EC_SIM_TYPE="spectre";
    EC_SIM_NAME="spectre";
    EC_SPICE_SIMPLIFY=1;
    EC_CHAR="ECSM-TIMING ECSM-POWER";
     
    #Specify the characterization inputs.
     
    SUBCKT="ceid_allStdCells_ELC.scs";
    MODEL="ll_rvt.scs";
    DESIGNS="INVX1";
    SETUP="/home/simop/cadence/umc65ll_lib/ELC/setup.std";
    PROCESS="typical";

     

    Command file:

    db_open ceid_vlsiLab_umc65ll_stdCells
     db_prepare -f
     db_gate
    db_spice -s spectre -keep_log -keep_wave
    db_wave -d INVX1 -p typical -id D0000
     db_output -lib out.lib -process typical -state
     db_close
     exit
     

     

     Setup file:

     Process typical {

            voltage     = 1.2   ; // as voltage

    temp        = 25    ; /* as temperature */

    Vtn     = 0.208 ;

    Vtp     = 0.208 ;

    } ;

     

    Process best {

            voltage     = 1.32   ; // as voltage

    temp        = 0    ; /* as temperature */

    Vtn     = 0.272  ;

    Vtp     = 0.272  ;

    } ;

     

    Process worst {

            voltage     = 1.08   ; // as voltage

    temp        = 125    ; /* as temperature */

    Vtn = 0.192  ;

    Vtp = 0.192  ;

    } ;

     

    Signal  std_cell {

    unit  = REL  ;          // relative value

    Vh    = 1.0  1.0 ;      // 100% rise/fall

    Vl    = 0.0  0.0 ;

    Vth   = 0.5  0.5 ;     // 50% rise/fall

    Vsh   = 0.8  0.8 ;

    Vsl   = 0.2  0.2 ;

    tsmax = 1.0n     ;     // maximum output slew rate

    } ;


    Simulation std_cell {

    transient    = 1.0n 100n  10p  ;

    bisec        = 6.0n 6.0n 10ps ;  // binary search

    resistance   = 10MEG;

    } ;

    Index   X1 {

    BSlew  = 0.0385N 0.5360N 2.0000N ;  // optional for binary search

    slew   = 0.0385N 0.0744N 0.1440N 0.2780N 0.5360N 1.0360N 2.0000N ;
    load   = 0.00082P 0.00330P 0.00842P 0.01848P 0.03861P 0.07870P 0.18975P ;
    } ;

     

    Index   XL {

    load   = 0.00041P 0.00165P 0.00421P 0.00924P 0.01930P 0.03935P 0.09488P ;
    } ;

     

    Index   X2 {

    load   = 0.00165P 0.00660P 0.01683P 0.03696P 0.07722P 0.15741P 0.37950P ;
    } ;

     

    Index   X3 {

    load   = 0.00248P 0.00990P 0.02524P 0.05544P 0.11583P 0.23612P 0.56925P ;
    } ;

    Index   X4 {

    load   = 0.00330P 0.01320P 0.03366P 0.07392P 0.15444P 0.31482P 0.75900P ;
    } ;

     

    Index   X6 {

    load   = 0.00495P 0.01980P 0.05049P 0.11088P 0.23166P 0.47223P 1.13850P ;
    } ;

    Index   X8 {

    load   = 0.00660P 0.02640P 0.06732P 0.14784P 0.30888P 0.62964P 1.51800P ;
    } ;

    Index   X12 {

    load   = 0.00990P 0.03960P 0.10098P 0.22176P 0.46332P 0.94446P 2.27700P ;
    } ;

    Index   X16 {

    load   = 0.01320P 0.05280P 0.13464P 0.29568P 0.61776P 1.25928P 3.03600P ;
    } ;

    Index   X20 {

    load   = 0.01650P 0.06600P 0.16830P 0.36960P 0.77220P 1.57410P 3.79500P ;
    } ;

     

    Index   CK_SLW {

    bslew   = 0.0385N 0.5360N 1.0360N ;

    } ;

     

    Group   CK_SLW {

    PIN = *.CK ;

    } ;

     

    Group   XL {

    CELL = *XL ;

    } ;

    Group   X1 {

    CELL = *X1 ;

    } ;

    Group   X2 {

    CELL = *X2 ;

    } ;

    Group   X3 {

    CELL = *X3 ;

    } ;

    Group   X4 {

    CELL = *X4 ;

    } ;

    Group   X6 {

    CELL = *X6 ;

    } ;

    Group   X8 {

    CELL = *X8 ;

    } ;

    Group   X12 {

    CELL = *X12 ;

    } ;

    Group   X16 {

    CELL = *X16 ;

    }

    } ;

    Group   X20 {

    CELL = *X20 ;

    } ;

     

    Margin   m0 {

    setup   = 1.0 0.0 ;

    hold    = 1.0 0.0 ;

    release = 1.0 0.0 ;

    removal = 1.0 0.0 ;

    recovery = 1.0 0.0 ;

    width   = 1.0 0.0 ;

    delay   = 1.0 0.0 ;

    power   = 1.0 0.0 ;

    cap     = 1.0 0.0 ;

    } ;

     

    Nominal  n0 {

    delay   = 0.5 0.5 ; // as rise fall

    power   = 0.5 0.5 ;

    cap     = 0.5 0.5 ;

    } ;

     

    // Control Section

    //

     

    set process (best,typical,worst) {

    simulation = std_cell ;

    index      = X1    ;

    signal     = std_cell  ;

    margin     = m0    ;

    nominal    = n0    ;

    } ;

     

    set index  (best,typical,worst) {

            Group(XL)  = XL  ;

    //      Group(X1)  = X1  ;

            Group(X2)  = X2  ;

            Group(X3)  = X3  ;

            Group(X4)  = X4  ;

            Group(X6)  = X6  ;

            Group(X8)  = X8  ;

            Group(X12) = X12 ;

            Group(X16) = X16 ;

            Group(X20) = X20 ;

    Group(CK_SLW) = CK_SLW ;

    } ;


    Thanks in advance,

    Thodoros

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