ELC Simulation failed with status 512

 I am trying to create a standard cell library with transistor level model written in verilog A. 

I am getting the following output 

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
               Simulation Summary               
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
-------------+-------------+----------+--------------+-----------
-------------+-------------+----------+------------+-----------+------------
   DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
-------------+-------------+----------+------------+-----------+------------
INVX1          typical       D0000     SIMULATE     FAIL        all_cells_tfet
INVX1          typical       D0001     SIMULATE     FAIL        all_cells_tfet
-------------+-------------+----------+------------+----------

When I checked the log file for error. I see " Simulation failed with status 512".

What does this error mean? Can anyone help me fix this issue?

Thanks

 Rangha