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post-sim failed

cashen

Dear Experts.

 I gernerated a Netlist from Design Compiler and did P&R/Layout through Encounter 10.1. Then I sent this post-layout netlist to nvsim for post-sim.However, I failed in the ncsim (a bunch of x-states) and got some "hold time" violation warnings.

 After applying delay_mode_zero or delay_mode_unit, the simulation worked. The interesting thing is Encounter didn't give me any violations (setup, hold, cap, transition, or fanout). The primetime also not showing any timing violations.

 Could anybody advise me how to fix this issue? Which constraints should I try during the synthesis stage?

 really appreciate,

 CA

  • 1.  Did you use back-annotated SDF in your post-sim? If not, this will probably cause timing violations in the post-sim.

    2. Do you have signals in your design that cross clock domains? If so, you may see x-states and timing

    violation warnings when the signals go through the synchronizers. You can suppress  the warnings using

    the $disable_warnings directive: $disable_warnings("timing", <path to synchronizer register> );

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