Stats

Locked Locked
Replies 0
Subscribers 91
Views 12655
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Resampled clock defintion problem in SDC file.

Hi,

In my design, there is a slow clock and a fast clock. Resampling the slow clock by the fast clock, I can get a generated clock. But I don't know how to define this generated resampled clock, and the timing constraints with other two clocks in the SDC file used in RTL Compiler and EDI 9.1.

Could you please help me about this problem?

Thanks a lot.

Best Regards,

Xuefei

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.