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ELC alf2vhdl error: Unexpected setuphold

Halo,

I've characterized a biphase enable flip flop with scan using ELC.

The alf2vhdl command is unable to write out a VITAL Timing file for the flip flop, and gives the error as given in the thread title.

This is very confusing since the alf2veri command writes out a verilog timing file with ease.

Unfortunately I need the VHDL VITAL file, is there another way to write this file, or perhaps a way to convert the verilog timing file into vhdl?

Thanks

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