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Issue with Pipeline Flops Placement

raj7783
Hi All, In my design there are many pipeline flops, they are introduced in the netlist to compensate long nets. When i do placeDesign in EDI 10.12.00, tool is placing pipeline registers closely leading to timing violations. I need to spread these pipeline flops. Is there any command which can do this? Does EDI understand pipeline flops and palce them at equidistance? Thanks in Advance

  • Please see the following solution for an explanation on how to define and place pipeline registers:

    http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11642648

     

  • Thanks Wally, But i dont want to do any re-synthesis. I have a group 512 bit registers in the deisgn which are already pipelined with another set of 512 bit registers. i want to tool place such pipelined registers at equidistant as they are getting placed closer now.

  • I believe you should be able to follow the flow in the solution but skip the step where you add the registers into your netlist since you already have this done. For example, you would use createPipelineNetGroup to define the start/stop points. Then run placePipeline to place the cells.

    Hope this helps

    Brian

  • I have followed it and implemented it for the flops which are existing the in the netlist but it doesnt work. I have given it as below createPipelineNetGroup netGroup1 -startTerm TopName/ModuleName/FlopName1/Q -endTerm TopName/ModuleName/FlopName2/D EDI returns with below line Added [0] net(s) in the net-group [netGroup1] It shows that its not creating the pipeline group. I have tried it may times but did not work . can you please help me out with this.

  • I'm not sure why this is not working for you assuming the connectivity is correct (i.e. there is connectivity path between these pins). If you're not able to debug this I recommend opening a Service Request through http://support.cadence.com so an AE can assist you.

    Thanks,

    Brian

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