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SOC Encounter :: LEF File load Failed

Sohaib Qazi

Hi

I am using SoC Encounter 10.1. While importing the design I load the netlist file (i.e. *.v file) and then add the LEF file to the list.

When I press OK then I get this error.

**ERROR: (ENCSYT-16013):
/sw/cadence/libraries/cmos065_522-2/CORL65LPSVT_5.1/CADENCE/LEF/
CORL65LPSVT_soc.lef failed

I am unable to resolve this issue.

Any suggestions ?

Thanks,

Qazi

Parents

  •  Apparently it is still a tech lef problem, because, for example:

    "#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000"

    shows that either your tech lef file is badly defined, or that encounter is using a default value.

     As stated by Kari previously, this type of information (layer height, spacing, via rules, etc...) is defined in the technology .lef file. To be sure you have such information, just open the.lef files you are using and search for layers definitions looking like that:

    LAYER M1

       TYPE ROUTING;

       DIRECTION HORIZONTAL;

       PITCH 0.4;

       HEIGHT 1.32;

       THICKNESS 0.42;

       ...

    END M1

     If none of the .lef files you are using have such definitions, then you are still missing something. I would advise you to dig a bit into the directory in which you have your technology/library files to find it.

     Also, it may be the order of your lef files that is not correct. In the Import Design form, the correct order is to specify first the tech .lef file, then the stdcell .lef file (if in a separate file), then the block .lef files.

     If everything else fail, then go back to step 1: ask your vendor/foundry to provide you this tech .lef.

Reply

  •  Apparently it is still a tech lef problem, because, for example:

    "#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000"

    shows that either your tech lef file is badly defined, or that encounter is using a default value.

     As stated by Kari previously, this type of information (layer height, spacing, via rules, etc...) is defined in the technology .lef file. To be sure you have such information, just open the.lef files you are using and search for layers definitions looking like that:

    LAYER M1

       TYPE ROUTING;

       DIRECTION HORIZONTAL;

       PITCH 0.4;

       HEIGHT 1.32;

       THICKNESS 0.42;

       ...

    END M1

     If none of the .lef files you are using have such definitions, then you are still missing something. I would advise you to dig a bit into the directory in which you have your technology/library files to find it.

     Also, it may be the order of your lef files that is not correct. In the Import Design form, the correct order is to specify first the tech .lef file, then the stdcell .lef file (if in a separate file), then the block .lef files.

     If everything else fail, then go back to step 1: ask your vendor/foundry to provide you this tech .lef.

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