I am using SoC Encounter 10.1. While importing the design I load the netlist file (i.e. *.v file) and then add the LEF file to the list.
When I press OK then I get this error.
I am unable to resolve this issue.
Any suggestions ?
There are no site rows in your design (and also, what are the blocks you say are missing? standard cells? power rings?)
I still find your tech lef strange. If for example the unit defined is the micron, we see that you have a routing grid with a distance between the routing tracks (defined by the PITCH statement) of 10 microns, even though the default routing width (WIDTH statement) is 0.09 microns. The width can be more of course, but my point is that it seems illogical to allow a so small width with a distance a hundred times more important.