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Error while reading Verilog File [Encounter 10.11]

nisshu

 Hi

 I am trying to import an Gate level design in Encounter but while reading the file it shows following error

**ERROR: (ENCVL-319):   vinst (buf_dummy__859) for pcell (iu3_nwin8_isets4_dsets2_fpu0_v850_cp0_mac0_dsu1_nwp2_pclow2_notag0_index0_lddel1_irfwt0_disas1_tbuf1_pwd2_svt0_rstaddr0_smp3_fabtech29_clk2x0_1) cell (0) has 0 VTerms.

 

also it shows the waring 

**WARN: (ENCVL-324):    Module SNPS_CLOCK_GATE_HIGH_iu3_nwin8_isets4_dsets2_fpu0_v850_cp0_mac0_dsu1_nwp2_pclow2_notag0_index0_lddel1_irfwt0_disas1_tbuf1_pwd2_svt0_rstaddr0_smp3_fabtech29_clk2x0_36 in ../verilog/mp.v will overwrite the previous definition in the same file.
 

but i checked there only one definition for that module in netlist.

Can somebody please help

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