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placeDesign runTime is 90+ Hrs.

gpremala

PlaceDesign is taking 90+ Hrs to finish the job, and after that if i check for checkPlace I am getting violations

Violations like Overlapping 20K+ instances, region/fence 0.4M Instances, Orientations 0.4M Instances

All the standard cells are placing together and they are not uniform distribution.

The Design has 2M instances and 400+ macros.

EDI version is 10.13

Please suggest me to resolve this issue.

 

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  • sureshm

     Hi gpremala, 

       There are multiple inputs you might want to check in the logfile & design partioning .. !! 

       to me , 2 M instances & 400 memories are bit on a high side to approach for Top-Down Flat Methodology.

       May I know the below items to understand the constraints of your design/block ?

       1) Design PPA targets?

       2) What is the initial utilization you have started with?

       3) Since 400 Memories are too high in number for any given block, Did you specify the soft blockages on the macro channels ?

       4) Are you targetting for MMMC mode if so , how many modes & corners ?

       5)  Is your block DEF shape is rectilinear or a regular shape with enough routing resources?

       6) Are there any gross timing violations ? What is the slack for the register to register timing in preplace analysis ?

       7) Did you manage the weights on the interface path groups?

    Thanks

    suresh  

Reply
  • sureshm

     Hi gpremala, 

       There are multiple inputs you might want to check in the logfile & design partioning .. !! 

       to me , 2 M instances & 400 memories are bit on a high side to approach for Top-Down Flat Methodology.

       May I know the below items to understand the constraints of your design/block ?

       1) Design PPA targets?

       2) What is the initial utilization you have started with?

       3) Since 400 Memories are too high in number for any given block, Did you specify the soft blockages on the macro channels ?

       4) Are you targetting for MMMC mode if so , how many modes & corners ?

       5)  Is your block DEF shape is rectilinear or a regular shape with enough routing resources?

       6) Are there any gross timing violations ? What is the slack for the register to register timing in preplace analysis ?

       7) Did you manage the weights on the interface path groups?

    Thanks

    suresh  

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