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regarding clocks

venkatramanan
After cts how we knows all flipflop get clocks? can u any one help me
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  • There are different methodologies that people follow for this, so I can only speak in general terms without knowing your flow specifically. In general, uncertainty may be bigger during preCTS, to model the skew you will get after CTS. Then, once you have clock trees, you can take the skew-modeling part out of the uncertainty to lower it a bit. But some flows leave the uncertainty the same throughout.

    For latency, once you have clock trees in, the real latency is always computed for the tree, so you don't have to do anything unless you're trying to model some source latency coming from off-chip or something. But you may use latency for I/O timing at the block level, if you're doing a hierarchical design. If that's the case, let me know, and I can provide some more details.

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  • There are different methodologies that people follow for this, so I can only speak in general terms without knowing your flow specifically. In general, uncertainty may be bigger during preCTS, to model the skew you will get after CTS. Then, once you have clock trees, you can take the skew-modeling part out of the uncertainty to lower it a bit. But some flows leave the uncertainty the same throughout.

    For latency, once you have clock trees in, the real latency is always computed for the tree, so you don't have to do anything unless you're trying to model some source latency coming from off-chip or something. But you may use latency for I/O timing at the block level, if you're doing a hierarchical design. If that's the case, let me know, and I can provide some more details.

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