• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Digital Implementation
  3. Wire width in verifyACLimit report

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 91
  • Views 13579
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Wire width in verifyACLimit report

SiddharthaUCSD
SiddharthaUCSD over 13 years ago

Hello,

I have a design routed using NDRs for all metal layers and each net is assigned to one of these NDRs. The NDRs for widths and spacings of metal layers are defined in a separate LEF, different from the technology LEF which defines rest of the other information.

I route using NanoRouter (routeDesign -globalDetail, perform extraction (extractRC), propagate a switching activity on all PIs, do a timing analysis (buildTimingGraph), perform EM analysis using verifyACLimit and then save the design and quit encounter.

Thereafter, I change some of the widths and spacings in the LEF that describes the NDR (the name of the rules are not changed) and relaunch encounter to restore the saved desig, load the LEF with NDRs (loadLeffile), perform extraction (extractRC), propagate a switching activity on all PIs, do a timing analysis (buildTimingGraph) and perform EM analysis using verifyACLimit. However, in the detailed report, I notice that none of the metal layer widths have changed. They are exactly the same as how it was routed before. I was expecting the widths to be updated from the LEF.

Please let me know how I can make it possible that verifyACLimit reports the updated wire widths without me having to re-route the design.

 Rgds,

Siddhartha.

  • Cancel
Parents
  • SiddharthaUCSD
    SiddharthaUCSD over 13 years ago

     HI Kari,

    Thanks for your response.

    I added the option -incremental to loadLefFile and now I am able to see the change in width in the verifyACLimit report when I perform rest of the steps the same. However, now I see the the Irms has increased for wire segments routed in the layers for which I widened the width. I thought it should decrease. Can you please let me know why am I observing this?

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • SiddharthaUCSD
    SiddharthaUCSD over 13 years ago

     HI Kari,

    Thanks for your response.

    I added the option -incremental to loadLefFile and now I am able to see the change in width in the verifyACLimit report when I perform rest of the steps the same. However, now I see the the Irms has increased for wire segments routed in the layers for which I widened the width. I thought it should decrease. Can you please let me know why am I observing this?

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information