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Flattening Netlist

bharat kurra over 13 years ago

Hi All,

I have a requirement to flatten my verilog netlist . I know the command "saveNetlist -flat" will do that.

But due to certain reasons i cant use that command . Can some one help me in a perl based or tcl based

script to flatten the netlist by taking the hierachical netlist and top module name as input

Thanks

Bharath K

crystee over 13 years ago

Hi,
You can flatten the netlist in the synthesis stage using DC (Design Compiler).In which their is an option of flattening your netlist.

Thanks
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grasshopper over 13 years ago

Hi crystee,
pretty much all self-respecting synthesis tools provide an 'ungroup' command for this purpose (RTL Compiler, Design Compiler, BuildGates, etc.). You can certainly use Perl, Python, etc. if you are so inclined but seems like wasted effort given that tools already support this
gh-
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