clock latency

Hi All,

For My subchip im seeing more min clock latency can you suggest me to reduce the min clock latency.Actually the max latency value is 1000ps and skew requirement 100ps. Min clock latency itself im seeing around 1600ps as a result the max latency is going around 1800ps.

Im not seeing the min latency for macro whare i can define macro model, im seeing min latency for flop. 

The width of subchip is some what high and the clock port is at center of left side.

And the block has 195 macros but placeble instances are less stdcell utilisation is 8%

Can i have the suggestions to reduce the min latency