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Clock Gating as a generated clock in SDC file

alexsieh

 Hello,

When there is clock gating logic, do I have to define the gated clock as a generated clock in my constraint file for a proper STA?

I don't know if anybody is familiar with this great book, but my question came up because I saw an example in the book "Static Timing Analysis for Nanometer Design: A practical Approach". Figure 7-12 shows an example where a clock is gated by the output of a flip-flop and then they wrote a SDC constraint to define the gated clock. See below:

create_clock 0.1 [get_ports SYS_CLK]
# Create a master clock of period 100ps with 50% duty cycle.
create_generated_clock -name CORE_CLK -divide_by 1 -source SYS_CLK [get_pins UAND1/Z]
# Create a generated clock called CORE_CLK at the output of the and cell and the clock

The book says: "Figure 7-12 shows an example where the clock SYS_CLK is gated by the output of a flip-flop. Since the output of the flip-flop may not be a constant, one way to handle this situation is to define a generated clock at the output of the and cell which is identical to the input clock."

 Must I define all gated clocks as new generated clocks in my SDC file?

The book mentiones that is one way to handle the situation, what are other ways to handle this situation?

Your input is much appreciated.

Sincerely,

AS

  • The other way to constraint clock gating and check that output of the gating cell is not clipped clock, you can use 

    set_clock_gating_check -setup xx -hold xx [get_clock CLK] 

    in your SDC.

     

     

  • Thanks, I appreciate the input. Can you explain more? these are obviously different commands and perform different tasks, so i don't quite understand how one may justify the absence of another in this case.

    Unless I use create_generated_clock command, I wonder if the EDA tool will know the shape of the gated clock waveform to perform timing analysis on the subsequent timing paths. Many clock gating logic are too complex (eg.: mux, xor logic) for a EDA tool to infer the gated clock waveform. By using set_clock_gating_check command, I believe I only guarantee that the gate enable signal switches correctly to avoid clock glitches (which is very important), but I still may encounter problems for timing analysis because of an undefined waveform of the gated clock. (that's where the create_generated_clock comes in). Does anybody agree with my thoughts?

    I am trying to find a reason why someone would define the output of a gated clock as a derived clock as shown in the book example. any more inputs? can anyone tell me if the book example is a common rule-of-thumb practice?

    Best Regards,

    AS

  • in reply to alexsieh

    Sorry to reply to an old thread. 

    I have a similar question. I have a SOC received from outside and it instantiates a number of latch based CG elements. Some gates a negated version of primary clock. 
    Is it a must to define a clock using create_generated_clock during synthesis in latest DC or RC? 

    Since the tool nowadays can insert CG elements automatically, would it be able to recognize those gated and inverted clocks and generate constraints automatically? 

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