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How to get desired clock skew during CTS?

I have a clock that is driving thousands of ffs and the CTS could build a well-balanced tree with about 6ns insertion delay for me. However, to resolve the reg2out timing violations, I like to launch some signals earlear and therefor hope to have shorter clock tree insertion delay (say, 2 ns) for about ten registers (I know their instance names). What is the easiest way to achive this during CTS stage?

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Tongju over 13 years ago

I figured out the solution: "MacroModel" will do the job!
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Tongju over 13 years ago

I figured out the solution: "MacroModel" will do the job!
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