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Regarding Clock Spec file

Ganga111AtFPS

 Hi I have some doubts in spec file declaration.

MaxDelay =?

MinDelay =?

MaxSkew =?

SinkMaxTran =?

BufMaxTran =?

RootInputTran =?

How can we decide and on what basis we decide those values ? Are those values design dependent ?

AFTER CTS::

1) How can we get know that all flops are getting clock?

I mean the flops in netlist and the clocked flops after CTS should be equal inorder to ensure that all flops are getting clock.

2) What is the procedure to decide the no. of  clocked flops in a design aftet CTS ? Is there any command to perform this operaton ?

3) can the encounter tool creates through pin for generated clocks inorder to supply the clock for the flops which are triggered by generated clock ? 

4) How can we know the max skew in our design from clock.report file ? 

  • Hi,

    All the clock tree spec file entries are documented in the EDI User Guide, "Synthesizing Clock Trees" chapter.

    Here's a summary of those you mentioned above:

    MaxDelay = maximum phase delay constraint (default 10 ns)

    MinDelay = minimum phase delay constraint (default 0 ns)

    MaxSkew = maximum skew between sinks (default 300ps)

    SinkMaxTran = maximum input transition time constraint for sinks (default 400ps)

    BufMaxTran = maximum input transition time constraint for buffers (default 400ps)

    RootInputTran = input transition time for input pins/ports (overrides SDC set_input_transition)

    Cheers,

    Chris

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