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Regarding clock spec file

Ganga111AtFPS

Hi,

I've the following doubt in selecting clock inverters or clock buffers:

 Q) on what basis we choose this much of high drive cells can be used to build clock tree?

is this design dependent like gate count of design and frequency of operation?

Generally I always prefer to use X8 and X12.Why can'n we use low drive like X4 etc..Is there any problem if i choose low drive cells?

Can any body give some clear explanation for the above question?

Parents

  • Our vendor has strict technology node dependant SinkMaxTran & BufMaxTran rules.
    The early / late clock derating factors used to calculate On Chip Variation are characterized within these input transition boundaries.
    Break the clock input transition rules and your STA timing margins may not be valid. ( not a warm fuzzy feeling at tapeout )

     

    Shawn

Reply

  • Our vendor has strict technology node dependant SinkMaxTran & BufMaxTran rules.
    The early / late clock derating factors used to calculate On Chip Variation are characterized within these input transition boundaries.
    Break the clock input transition rules and your STA timing margins may not be valid. ( not a warm fuzzy feeling at tapeout )

     

    Shawn

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