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Regarding clock spec file

Ganga111AtFPS over 13 years ago

Hi,

I've the following doubt in selecting clock inverters or clock buffers:

Q) on what basis we choose this much of high drive cells can be used to build clock tree?

is this design dependent like gate count of design and frequency of operation?

Generally I always prefer to use X8 and X12.Why can'n we use low drive like X4 etc..Is there any problem if i choose low drive cells?

Can any body give some clear explanation for the above question?

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Scrivner over 13 years ago

We always add a good bit of clock uncertainty in our constraints to add extra margin on top of OCV derating. That way if we are just barely meeting timing, we know we still have a good bit of margin built in.
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Scrivner over 13 years ago

We always add a good bit of clock uncertainty in our constraints to add extra margin on top of OCV derating. That way if we are just barely meeting timing, we know we still have a good bit of margin built in.
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