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to overcome timing slack UNCUSTRAINED for combinational circuit in synthesis report

hi,

i am designing combinational cicuit design, wrote sdc file using virtual clock and it is showing timing slack unconstrained,can any one help me in this regard

grasshopper over 13 years ago

Hi Andhra,
please share your constraints. I suspect you are only clocking the inputs or the outputs when both need a clock reference

gh-
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