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Synthsis of VHDL-2008 on RC

shahein

Dear All,

 I developed a design based on VHDL-2008 standard, I can compile it and simulate it pretty fine using NClaunch and SimVision, respectivly. 

However, I am not able to synthesis the same code using RC.

I am using Cadence 5 flow with RC v10.1.

What is your recommendations to overcome this issue.

In waiting for your constructive feedbacks.

Regards.

  • Hi shahein,

    I suggest you contact your local AE and identify the VHDL-2008 constructs you are seeking support for. VHDL-2008 is not fully supported yet. In fact, I would caution you most EDA tools out there do not FULLY support VHDL-2008

     gh-

     

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