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EDI -> Empty Modules

Terry2000 over 12 years ago

Hello,

First run through EDI 12.00 and I'm having a few teething problems.

Successfully synthesised the RTL to verilog netlist but when I import the design I'm getting the following warnings (all standard cells are in the verilog netlist are listed, I've trucated the listing for the post).

I've checked the LEF and the cells are included.

Any ideas what I'm doing wrong?

**WARN: (ENCDB-2504):    Cell OR6M2XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell OR4M1XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell NR3M1XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell AO31M2XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell DFQRM1XM is instantiated in the Verilog netlist, but is not defined.
WARN: (EMS-63):       Message <ENCDB-2504> has exceeded the default message display limit of 20.

Found empty module (OR6M2XM).
Found empty module (OR4M1XM).
Found empty module (NR3M1XM).
Found empty module (AO31M2XM).
Found empty module (DFQRM1XM).
Starting recursive module instantiation check.
No recursion found.
Term dir updated for 0 vinsts of 85 cells.
Building hierarchical netlist for Cell hlt5000_toplevel ...
*** Netlist is unique.
** info: there are 91 modules.
** info: there are 0 stdCell insts.

Parents

Terry2000 over 12 years ago

Hello,
Thanks for your reply, good point because I can't see the lef being read in the log. The lef file however is being correctly add to the form.
I've added a snippet of the log file and a snippet of the lef file. I'm no expert on lef files, does it look correct?
Log file ->
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist 'r2g_output/r2g.v'
Inserting temporary buffers to remove assignment statements.
*** Memory Usage v#16 (Current mem = 368.211M, initial mem = 73.984M) ***
*** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=368.2M) ***
Set top cell to hlt5000_toplevel.
*** End library_loading (cpu=0.00min, mem=0.0M, fe_cpu=0.09min, fe_real=1.43min, fe_mem=368.2M) ***
{DETAILMESSAGE}**WARN: (ENCDB-2504):    Cell OR6M2XM is instantiated in the Verilog netlist, but is not defined.
LEF file ->
MACRO OR6M2XM
    CLASS CORE ;
    FOREIGN OR6M2XM 0 0 ;
    ORIGIN 0.0000 0.0000 ;
    SIZE 2.6000 BY 1.4000 ;
    SYMMETRY X Y ;
    SITE CORE ;
    PIN B
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 2.0500 0.5850 2.1550 1.0400 ;
        END
    END B
    PIN A
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 2.4400 0.4550 2.5500 0.8700 ;
        END
    END A
    PIN C
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 1.8000 0.6500 1.9600 0.9900 ;
        END
    END C
    PIN D
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 0.6500 0.6100 0.9600 0.7900 ;
        END
    END D
    PIN E
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 0.3900 0.6200 0.5500 1.0000 ;
        END
    END E
    PIN F
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 0.0500 0.6100 0.2600 0.8500 ;
        END
    END F
    PIN Z
        DIRECTION OUTPUT ;
        ANTENNADIFFAREA 0.1436 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 1.2500 0.2600 1.5250 0.3900 ;
        RECT 1.2500 0.2600 1.3550 1.1900 ;
        END
    END Z
    PIN VDD
        DIRECTION INOUT ;
        USE POWER ;
        SHAPE ABUTMENT ;
        PORT
        LAYER ME1 ;
        RECT 0.0000 1.2950 2.6000 1.5050 ;
        RECT 1.5800 0.8800 1.7100 1.5050 ;
        RECT 0.9650 1.0600 1.0950 1.5050 ;
        RECT 0.0550 1.0300 0.1850 1.5050 ;
        END
    END VDD
    PIN VSS
        DIRECTION INOUT ;
        USE GROUND ;
        SHAPE ABUTMENT ;
        PORT
        LAYER ME1 ;
        RECT 0.0000 -0.1050 2.6000 0.1050 ;
        RECT 2.4350 -0.1050 2.5450 0.3450 ;
        RECT 1.8750 -0.1050 2.0450 0.3050 ;
        RECT 0.8950 -0.1050 1.0250 0.3250 ;
        RECT 0.3150 -0.1050 0.4450 0.3250 ;
        END
    END VSS
    OBS
        LAYER ME1 ;
        RECT 0.0550 0.1950 0.1850 0.5200 ;
        RECT 0.5750 0.1950 0.7300 0.5200 ;
        RECT 0.0550 0.4300 1.1500 0.5200 ;
        RECT 1.0600 0.4300 1.1500 0.9700 ;
        RECT 0.7550 0.8800 1.1500 0.9700 ;
        RECT 0.7550 0.8800 0.8650 1.1700 ;
        RECT 1.6200 0.1950 1.7650 0.4950 ;
        RECT 2.1350 0.1950 2.3450 0.4950 ;
        RECT 1.6200 0.3950 2.3450 0.4950 ;
        RECT 1.6200 0.1950 1.7100 0.7000 ;
        RECT 1.4650 0.5700 1.7100 0.7000 ;
        RECT 2.2450 0.1950 2.3450 1.1500 ;
        RECT 2.2450 1.0200 2.5450 1.1500 ;
        LAYER SPSHVT ;
        RECT 0.0000 0.0000 2.6000 1.4000 ;
    END
END OR6M2XM
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Terry2000 over 12 years ago

Hello,
Thanks for your reply, good point because I can't see the lef being read in the log. The lef file however is being correctly add to the form.
I've added a snippet of the log file and a snippet of the lef file. I'm no expert on lef files, does it look correct?
Log file ->
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist 'r2g_output/r2g.v'
Inserting temporary buffers to remove assignment statements.
*** Memory Usage v#16 (Current mem = 368.211M, initial mem = 73.984M) ***
*** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=368.2M) ***
Set top cell to hlt5000_toplevel.
*** End library_loading (cpu=0.00min, mem=0.0M, fe_cpu=0.09min, fe_real=1.43min, fe_mem=368.2M) ***
{DETAILMESSAGE}**WARN: (ENCDB-2504):    Cell OR6M2XM is instantiated in the Verilog netlist, but is not defined.
LEF file ->
MACRO OR6M2XM
    CLASS CORE ;
    FOREIGN OR6M2XM 0 0 ;
    ORIGIN 0.0000 0.0000 ;
    SIZE 2.6000 BY 1.4000 ;
    SYMMETRY X Y ;
    SITE CORE ;
    PIN B
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 2.0500 0.5850 2.1550 1.0400 ;
        END
    END B
    PIN A
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 2.4400 0.4550 2.5500 0.8700 ;
        END
    END A
    PIN C
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 1.8000 0.6500 1.9600 0.9900 ;
        END
    END C
    PIN D
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 0.6500 0.6100 0.9600 0.7900 ;
        END
    END D
    PIN E
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 0.3900 0.6200 0.5500 1.0000 ;
        END
    END E
    PIN F
        DIRECTION INPUT ;
        ANTENNAMODEL OXIDE1 ;
        ANTENNAGATEAREA 0.0252 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 0.0500 0.6100 0.2600 0.8500 ;
        END
    END F
    PIN Z
        DIRECTION OUTPUT ;
        ANTENNADIFFAREA 0.1436 LAYER ME1 ;
        PORT
        LAYER ME1 ;
        RECT 1.2500 0.2600 1.5250 0.3900 ;
        RECT 1.2500 0.2600 1.3550 1.1900 ;
        END
    END Z
    PIN VDD
        DIRECTION INOUT ;
        USE POWER ;
        SHAPE ABUTMENT ;
        PORT
        LAYER ME1 ;
        RECT 0.0000 1.2950 2.6000 1.5050 ;
        RECT 1.5800 0.8800 1.7100 1.5050 ;
        RECT 0.9650 1.0600 1.0950 1.5050 ;
        RECT 0.0550 1.0300 0.1850 1.5050 ;
        END
    END VDD
    PIN VSS
        DIRECTION INOUT ;
        USE GROUND ;
        SHAPE ABUTMENT ;
        PORT
        LAYER ME1 ;
        RECT 0.0000 -0.1050 2.6000 0.1050 ;
        RECT 2.4350 -0.1050 2.5450 0.3450 ;
        RECT 1.8750 -0.1050 2.0450 0.3050 ;
        RECT 0.8950 -0.1050 1.0250 0.3250 ;
        RECT 0.3150 -0.1050 0.4450 0.3250 ;
        END
    END VSS
    OBS
        LAYER ME1 ;
        RECT 0.0550 0.1950 0.1850 0.5200 ;
        RECT 0.5750 0.1950 0.7300 0.5200 ;
        RECT 0.0550 0.4300 1.1500 0.5200 ;
        RECT 1.0600 0.4300 1.1500 0.9700 ;
        RECT 0.7550 0.8800 1.1500 0.9700 ;
        RECT 0.7550 0.8800 0.8650 1.1700 ;
        RECT 1.6200 0.1950 1.7650 0.4950 ;
        RECT 2.1350 0.1950 2.3450 0.4950 ;
        RECT 1.6200 0.3950 2.3450 0.4950 ;
        RECT 1.6200 0.1950 1.7100 0.7000 ;
        RECT 1.4650 0.5700 1.7100 0.7000 ;
        RECT 2.2450 0.1950 2.3450 1.1500 ;
        RECT 2.2450 1.0200 2.5450 1.1500 ;
        LAYER SPSHVT ;
        RECT 0.0000 0.0000 2.6000 1.4000 ;
    END
END OR6M2XM
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