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EDI -> Empty Modules

Terry2000

Hello, 

First run through EDI 12.00 and I'm having a few teething problems.

Successfully synthesised the RTL to verilog netlist but when I import the design I'm getting the following warnings (all standard cells are in the verilog netlist are listed, I've trucated the listing for the post).

I've checked the LEF and the cells are included.

 Any ideas what I'm doing wrong?

**WARN: (ENCDB-2504):    Cell OR6M2XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell OR4M1XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell NR3M1XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell AO31M2XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell DFQRM1XM is instantiated in the Verilog netlist, but is not defined.
WARN: (EMS-63):       Message <ENCDB-2504> has exceeded the default message display limit of 20.

Found empty module (OR6M2XM).
Found empty module (OR4M1XM).
Found empty module (NR3M1XM).
Found empty module (AO31M2XM).
Found empty module (DFQRM1XM).
Starting recursive module instantiation check.
No recursion found.
Term dir updated for 0 vinsts of 85 cells.
Building hierarchical netlist for Cell hlt5000_toplevel ...
*** Netlist is unique.
** info: there are 91 modules.
** info: there are 0 stdCell insts.
 

Parents

  • Hello,

    I've had a look at the cmd file generated using the file->import design. If I've understood correctly for some reason the init_lef_file variable is being set correctly then cleared.

    *** Memory pool thread-safe mode activated.
    <CMD> set conf_ioOri R0
    <CMD> set defHierChar /
    <CMD> set delaycal_input_transition_delay 0.1ps
    Set Input Pin Transition Delay as 0.1 ps.
    <CMD> set init_assign_buffer 1
    <CMD> set init_import_mode { -keepEmptyModule 1 -timerMode 1 -treatUndefinedCellAsBbox 0}
    <CMD> set init_lef_file /libs/UMC/UMxxxLSCSPMVBDS_A01/lef/uxxxlscspmvbds.lef
    <CMD> set init_oa_search_lib {}
    <CMD> set init_top_cell toplevel
    <CMD> set init_verilog r2g_output/r2g.v
    <CMD> set lsgOCPGainMult 1.000000
    <CMD> set rtl_vhdl_list {{WORK {WORK ../RTL/adc_interface.vhd ../RTL/fuse_control.vhd ../RTL/fuse_interface.vhd ../RTL/i2c_interface.vhd ../RTL/package.vhd}} {TEMP {}}}
    <CMD> set init_lef_file {}
    <CMD> init_design
    Reading netlist ...

     I entered the commands on the command line without the set init_lef_file {} and it's now trying to load the lef, it's moaning about it but at least  it's attempting to load. Thanks again for your help. 

    Loading LEF file /libs/UMC/UMxxxLSCSPMVBDS_A01/lef/uxxxlscspmvbds.lef...
    **ERROR: (ENCLF-328):   The layer 'ME1' specified in macro pin 'XOR4M8XM.A' does                                                                                    not exist
    **ERROR: (ENCLF-53):    The layer 'ME1' referenced in pin 'A' in macro 'XOR4M8XM                                                                                   ' is not found in the database. A layer must be defined in the LEF technology LA                                                                                   YER section before it can be referenced.

Reply

  • Hello,

    I've had a look at the cmd file generated using the file->import design. If I've understood correctly for some reason the init_lef_file variable is being set correctly then cleared.

    *** Memory pool thread-safe mode activated.
    <CMD> set conf_ioOri R0
    <CMD> set defHierChar /
    <CMD> set delaycal_input_transition_delay 0.1ps
    Set Input Pin Transition Delay as 0.1 ps.
    <CMD> set init_assign_buffer 1
    <CMD> set init_import_mode { -keepEmptyModule 1 -timerMode 1 -treatUndefinedCellAsBbox 0}
    <CMD> set init_lef_file /libs/UMC/UMxxxLSCSPMVBDS_A01/lef/uxxxlscspmvbds.lef
    <CMD> set init_oa_search_lib {}
    <CMD> set init_top_cell toplevel
    <CMD> set init_verilog r2g_output/r2g.v
    <CMD> set lsgOCPGainMult 1.000000
    <CMD> set rtl_vhdl_list {{WORK {WORK ../RTL/adc_interface.vhd ../RTL/fuse_control.vhd ../RTL/fuse_interface.vhd ../RTL/i2c_interface.vhd ../RTL/package.vhd}} {TEMP {}}}
    <CMD> set init_lef_file {}
    <CMD> init_design
    Reading netlist ...

     I entered the commands on the command line without the set init_lef_file {} and it's now trying to load the lef, it's moaning about it but at least  it's attempting to load. Thanks again for your help. 

    Loading LEF file /libs/UMC/UMxxxLSCSPMVBDS_A01/lef/uxxxlscspmvbds.lef...
    **ERROR: (ENCLF-328):   The layer 'ME1' specified in macro pin 'XOR4M8XM.A' does                                                                                    not exist
    **ERROR: (ENCLF-53):    The layer 'ME1' referenced in pin 'A' in macro 'XOR4M8XM                                                                                   ' is not found in the database. A layer must be defined in the LEF technology LA                                                                                   YER section before it can be referenced.

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